1. Field of the Invention
The present invention relates to a device for producing two clock pulse trains to serve as a clock pulse supply for digital semiconductor circuits, and in particular for producing such clock pulse trains from a periodic input signal having any waveform, and in which the clock pulse trains have the same period but have duty cycles which are separated by down time when the pulses are aligned.
2. Description of the Prior Art
A generator for the clock control of monolithically integrated digital semiconductor circuits is disclosed in German OS No. 23 45 837 which produces two series of periodic digital pulses. The pulses of the two series thus produced are phase shifted opposite one another by the same time value.
The pulses thus produced are of the conventional rectangular-shaped profile having two different voltage states, one of which corresponds to the logical zero and the other to the logical one and in which the duty cycle of the individual pulse is associated with only one of these logical states. The other state generally corresponds to the information less state.
Another clock pulse circuit is disclosed in German OS No. 27 13 319 in which a pulse converter which operates from an input of periodic electrical pulses, operates on the input pulses to produce two separate output pulse trains having a defined time relationship such that, when aligned, the two output pulse series have duty cycles which are separated from each other by down time. Interfering overlapping of the duty cycles in the digital circuit which is controlled by the clock is thus significantly minimized, because the presence of the down time between the duty cycles compensates for the effect of transit time differences in the controlled circuit.